79abb8f140
Bump & refresh patches for all 4.4 targets. Compile & run tested: ar71xx Archer C7 v2 Signed-off-by: Kevin Darbyshire-Bryant <kevin@darbyshire-bryant.me.uk>
68 lines
1.8 KiB
Diff
68 lines
1.8 KiB
Diff
From 57d147c02fdcbae5e61ba322d51c5734f9511fd7 Mon Sep 17 00:00:00 2001
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From: Mingkai Hu <mingkai.hu@nxp.com>
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Date: Mon, 26 Sep 2016 14:19:32 +0800
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Subject: [PATCH 134/141] pci/layerscape: add LUT DBG reigster offset member
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commit 59ab37d6f46356a5b9755fcec74b23616dfdd62f
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[doesn't apply pm part]
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Different chip have different LUT debug register offset,
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so add a member to avoid macro redifinition.
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Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
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Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
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Integrated-by: Yutang Jiang <yutang.jiang@nxp.com>
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---
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drivers/pci/host/pci-layerscape.c | 8 ++++++--
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1 file changed, 6 insertions(+), 2 deletions(-)
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--- a/drivers/pci/host/pci-layerscape.c
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+++ b/drivers/pci/host/pci-layerscape.c
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@@ -41,6 +41,7 @@
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struct ls_pcie_drvdata {
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u32 lut_offset;
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u32 ltssm_shift;
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+ u32 lut_dbg;
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struct pcie_host_ops *ops;
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};
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@@ -134,7 +135,7 @@ static int ls_pcie_link_up(struct pcie_p
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struct ls_pcie *pcie = to_ls_pcie(pp);
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u32 state;
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- state = (ioread32(pcie->lut + PCIE_LUT_DBG) >>
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+ state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
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pcie->drvdata->ltssm_shift) &
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LTSSM_STATE_MASK;
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@@ -196,24 +197,28 @@ static struct ls_pcie_drvdata ls1021_drv
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static struct ls_pcie_drvdata ls1012_drvdata = {
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.lut_offset = 0xC0000,
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.ltssm_shift = 24,
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+ .lut_dbg = 0x7fc,
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.ops = &ls_pcie_host_ops,
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};
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static struct ls_pcie_drvdata ls1043_drvdata = {
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.lut_offset = 0x10000,
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.ltssm_shift = 24,
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+ .lut_dbg = 0x7fc,
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.ops = &ls_pcie_host_ops,
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};
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static struct ls_pcie_drvdata ls1046_drvdata = {
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- .lut_offset = 0x10000,
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+ .lut_offset = 0x80000,
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.ltssm_shift = 24,
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+ .lut_dbg = 0x407fc,
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.ops = &ls_pcie_host_ops,
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};
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static struct ls_pcie_drvdata ls2080_drvdata = {
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.lut_offset = 0x80000,
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.ltssm_shift = 0,
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+ .lut_dbg = 0x7fc,
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.ops = &ls_pcie_host_ops,
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};
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