0ea329fec4
Weijie Gao has submitted an updated version of the patchset adding support for MT7986 and MT7981 to U-Boot. Use that v2 patchset. Changes of v2: - Add cpu driver for print_cpuinfo() - Fix NULL pointer dereference in mtk_image (was already fixed in OpenWrt) - Fix coding style - Minor changes https://patchwork.ozlabs.org/project/uboot/list/?series=316148 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
164 lines
4.9 KiB
Diff
164 lines
4.9 KiB
Diff
From ba6af13fd58c0ec418720d959152e0db47e91b02 Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Wed, 31 Aug 2022 19:04:19 +0800
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Subject: [PATCH 06/32] net: mediatek: use a struct to cover variations of all
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SoCs
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Using a single soc id to control different initialization and TX/RX flow
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for all SoCs is not extensible if more hardware variations are added in
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the future.
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This patch introduces a struct to replace the original mtk_soc to allow
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the driver be able handle newer hardwares.
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Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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drivers/net/mtk_eth.c | 56 ++++++++++++++++++++++++++++++-------------
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drivers/net/mtk_eth.h | 25 ++++++++++++++++++-
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2 files changed, 64 insertions(+), 17 deletions(-)
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--- a/drivers/net/mtk_eth.c
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+++ b/drivers/net/mtk_eth.c
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@@ -142,11 +142,15 @@ enum mtk_switch {
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SW_MT7531
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};
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-enum mtk_soc {
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- SOC_MT7623,
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- SOC_MT7629,
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- SOC_MT7622,
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- SOC_MT7621
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+/* struct mtk_soc_data - This is the structure holding all differences
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+ * among various plaforms
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+ * @caps Flags shown the extra capability for the SoC
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+ * @ana_rgc3: The offset for register ANA_RGC3 related to
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+ * sgmiisys syscon
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+ */
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+struct mtk_soc_data {
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+ u32 caps;
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+ u32 ana_rgc3;
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};
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struct mtk_eth_priv {
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@@ -171,7 +175,7 @@ struct mtk_eth_priv {
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int (*mmd_write)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg,
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u16 val);
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- enum mtk_soc soc;
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+ const struct mtk_soc_data *soc;
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int gmac_id;
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int force_mode;
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int speed;
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@@ -679,7 +683,7 @@ static int mt7530_setup(struct mtk_eth_p
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u32 val, txdrv;
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int i;
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- if (priv->soc != SOC_MT7621) {
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+ if (!MTK_HAS_CAPS(priv->soc->caps, MTK_TRGMII_MT7621_CLK)) {
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/* Select 250MHz clk for RGMII mode */
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mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG,
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ETHSYS_TRGMII_CLK_SEL362_5, 0);
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@@ -1108,9 +1112,8 @@ static int mtk_phy_probe(struct udevice
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static void mtk_sgmii_init(struct mtk_eth_priv *priv)
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{
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/* Set SGMII GEN2 speed(2.5G) */
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- clrsetbits_le32(priv->sgmii_base + ((priv->soc == SOC_MT7622) ?
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- SGMSYS_GEN2_SPEED : SGMSYS_GEN2_SPEED_V2),
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- SGMSYS_SPEED_2500, SGMSYS_SPEED_2500);
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+ setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
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+ SGMSYS_SPEED_2500);
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/* Disable SGMII AN */
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clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
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@@ -1182,7 +1185,8 @@ static void mtk_mac_init(struct mtk_eth_
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mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr);
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}
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- if (priv->soc == SOC_MT7623) {
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+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC1_TRGMII) &&
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+ !MTK_HAS_CAPS(priv->soc->caps, MTK_TRGMII_MT7621_CLK)) {
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/* Lower Tx Driving for TRGMII path */
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for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
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mtk_gmac_write(priv, GMAC_TRGMII_TD_ODT(i),
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@@ -1431,7 +1435,11 @@ static int mtk_eth_of_to_plat(struct ude
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ofnode subnode;
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int ret;
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- priv->soc = dev_get_driver_data(dev);
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+ priv->soc = (const struct mtk_soc_data *)dev_get_driver_data(dev);
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+ if (!priv->soc) {
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+ dev_err(dev, "missing soc compatible data\n");
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+ return -EINVAL;
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+ }
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pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
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@@ -1544,11 +1552,27 @@ static int mtk_eth_of_to_plat(struct ude
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return 0;
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}
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+static const struct mtk_soc_data mt7629_data = {
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+ .ana_rgc3 = 0x128,
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+};
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+
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+static const struct mtk_soc_data mt7623_data = {
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+ .caps = MT7623_CAPS,
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+};
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+
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+static const struct mtk_soc_data mt7622_data = {
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+ .ana_rgc3 = 0x2028,
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+};
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+
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+static const struct mtk_soc_data mt7621_data = {
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+ .caps = MT7621_CAPS,
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+};
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+
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static const struct udevice_id mtk_eth_ids[] = {
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- { .compatible = "mediatek,mt7629-eth", .data = SOC_MT7629 },
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- { .compatible = "mediatek,mt7623-eth", .data = SOC_MT7623 },
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- { .compatible = "mediatek,mt7622-eth", .data = SOC_MT7622 },
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- { .compatible = "mediatek,mt7621-eth", .data = SOC_MT7621 },
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+ { .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data },
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+ { .compatible = "mediatek,mt7623-eth", .data = (ulong)&mt7623_data },
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+ { .compatible = "mediatek,mt7622-eth", .data = (ulong)&mt7622_data },
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+ { .compatible = "mediatek,mt7621-eth", .data = (ulong)&mt7621_data },
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{}
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};
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--- a/drivers/net/mtk_eth.h
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+++ b/drivers/net/mtk_eth.h
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@@ -9,8 +9,31 @@
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#ifndef _MTK_ETH_H_
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#define _MTK_ETH_H_
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-/* Frame Engine Register Bases */
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#include <linux/bitops.h>
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+
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+enum mkt_eth_capabilities {
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+ MTK_TRGMII_BIT,
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+ MTK_TRGMII_MT7621_CLK_BIT,
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+
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+ /* PATH BITS */
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+ MTK_ETH_PATH_GMAC1_TRGMII_BIT,
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+};
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+
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+#define MTK_TRGMII BIT(MTK_TRGMII_BIT)
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+#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
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+
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+/* Supported path present on SoCs */
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+#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
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+
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+#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
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+
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+#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
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+
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+#define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK)
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+
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+#define MT7623_CAPS (MTK_GMAC1_TRGMII)
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+
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+/* Frame Engine Register Bases */
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#define PDMA_BASE 0x0800
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#define GDMA1_BASE 0x0500
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#define GDMA2_BASE 0x1500
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