0ea329fec4
Weijie Gao has submitted an updated version of the patchset adding support for MT7986 and MT7981 to U-Boot. Use that v2 patchset. Changes of v2: - Add cpu driver for print_cpuinfo() - Fix NULL pointer dereference in mtk_image (was already fixed in OpenWrt) - Fix coding style - Minor changes https://patchwork.ozlabs.org/project/uboot/list/?series=316148 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
136 lines
3.9 KiB
Diff
136 lines
3.9 KiB
Diff
From c53d249df9a75f77f5d0abb986a8913bc13070d0 Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Wed, 31 Aug 2022 19:05:09 +0800
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Subject: [PATCH 24/32] clk: mediatek: add infrasys clock mux support
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This patch adds infrasys clock mux support for mediatek clock drivers.
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Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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drivers/clk/mediatek/clk-mtk.c | 71 ++++++++++++++++++++++++++++++++++
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drivers/clk/mediatek/clk-mtk.h | 4 +-
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2 files changed, 74 insertions(+), 1 deletion(-)
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--- a/drivers/clk/mediatek/clk-mtk.c
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+++ b/drivers/clk/mediatek/clk-mtk.c
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@@ -303,6 +303,24 @@ static ulong mtk_topckgen_get_factor_rat
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return mtk_factor_recalc_rate(fdiv, rate);
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}
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+static ulong mtk_infrasys_get_factor_rate(struct clk *clk, u32 off)
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+{
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+ struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
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+ const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off];
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+ ulong rate;
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+
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+ switch (fdiv->flags & CLK_PARENT_MASK) {
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+ case CLK_PARENT_TOPCKGEN:
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+ rate = mtk_clk_find_parent_rate(clk, fdiv->parent,
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+ priv->parent);
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+ break;
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+ default:
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+ rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
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+ }
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+
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+ return mtk_factor_recalc_rate(fdiv, rate);
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+}
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+
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static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off)
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{
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struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
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@@ -331,6 +349,33 @@ static ulong mtk_topckgen_get_mux_rate(s
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return priv->tree->xtal_rate;
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}
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+static ulong mtk_infrasys_get_mux_rate(struct clk *clk, u32 off)
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+{
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+ struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
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+ const struct mtk_composite *mux = &priv->tree->muxes[off];
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+ u32 index;
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+
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+ index = readl(priv->base + mux->mux_reg);
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+ index &= mux->mux_mask << mux->mux_shift;
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+ index = index >> mux->mux_shift;
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+
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+ if (mux->parent[index] > 0 ||
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+ (mux->parent[index] == CLK_XTAL &&
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+ priv->tree->flags & CLK_BYPASS_XTAL)) {
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+ switch (mux->flags & CLK_PARENT_MASK) {
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+ case CLK_PARENT_TOPCKGEN:
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+ return mtk_clk_find_parent_rate(clk, mux->parent[index],
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+ priv->parent);
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+ break;
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+ default:
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+ return mtk_clk_find_parent_rate(clk, mux->parent[index],
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+ NULL);
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+ break;
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+ }
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+ }
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+ return 0;
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+}
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+
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static ulong mtk_topckgen_get_rate(struct clk *clk)
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{
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struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
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@@ -345,6 +390,25 @@ static ulong mtk_topckgen_get_rate(struc
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priv->tree->muxes_offs);
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}
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+static ulong mtk_infrasys_get_rate(struct clk *clk)
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+{
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+ struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
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+
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+ ulong rate;
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+
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+ if (clk->id < priv->tree->fdivs_offs) {
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+ rate = priv->tree->fclks[clk->id].rate;
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+ } else if (clk->id < priv->tree->muxes_offs) {
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+ rate = mtk_infrasys_get_factor_rate(clk, clk->id -
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+ priv->tree->fdivs_offs);
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+ } else {
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+ rate = mtk_infrasys_get_mux_rate(clk, clk->id -
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+ priv->tree->muxes_offs);
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+ }
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+
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+ return rate;
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+}
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+
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static int mtk_clk_mux_enable(struct clk *clk)
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{
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struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
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@@ -493,6 +557,13 @@ const struct clk_ops mtk_clk_topckgen_op
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.set_parent = mtk_common_clk_set_parent,
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};
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+const struct clk_ops mtk_clk_infrasys_ops = {
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+ .enable = mtk_clk_mux_enable,
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+ .disable = mtk_clk_mux_disable,
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+ .get_rate = mtk_infrasys_get_rate,
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+ .set_parent = mtk_common_clk_set_parent,
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+};
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+
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const struct clk_ops mtk_clk_gate_ops = {
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.enable = mtk_clk_gate_enable,
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.disable = mtk_clk_gate_disable,
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--- a/drivers/clk/mediatek/clk-mtk.h
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+++ b/drivers/clk/mediatek/clk-mtk.h
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@@ -28,7 +28,8 @@
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#define CLK_PARENT_APMIXED BIT(4)
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#define CLK_PARENT_TOPCKGEN BIT(5)
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-#define CLK_PARENT_MASK GENMASK(5, 4)
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+#define CLK_PARENT_INFRASYS BIT(6)
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+#define CLK_PARENT_MASK GENMASK(6, 4)
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#define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34
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@@ -220,6 +221,7 @@ struct mtk_cg_priv {
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extern const struct clk_ops mtk_clk_apmixedsys_ops;
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extern const struct clk_ops mtk_clk_topckgen_ops;
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+extern const struct clk_ops mtk_clk_infrasys_ops;
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extern const struct clk_ops mtk_clk_gate_ops;
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int mtk_common_clk_init(struct udevice *dev,
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