b1f21329d4
Qualcomm IPQ40xx SoC-s have a variant of QCA8337N switch built-in. It shares most of the stuff with its external counterpart, however it is modified for the SoC. Namely, it doesn't have second CPU port (Port 6), so it has 6 ports instead of 7. It also has no built-in PHY-s but rather requires external PSGMII based companion PHY-s (QCA8072 and QCA8075) for which it first needs to carry out calibration before using them. PSGMII has a SoC built-in PHY that is used to connect to the PHY-s which unfortunately requires some magic values as the datasheet doesnt document the bits that are being set or the register at all. Since its built-in it is MMIO like other peripherals and doesn't have its own MDIO bus but depends on the SoC provided one. CPU connection is at Port 0 and it uses some kind of a internal connection and no traditional RGMII/SGMII. It also doesn't use in-band tagging like other qca8k switches so a shinfo based tagger is used. This is based on the current OpenWrt qca8k version that has been imported from generic target. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
57 lines
2.1 KiB
Diff
57 lines
2.1 KiB
Diff
From b5f71652b85a85ea53162e9e2b760b84fd0d254f Mon Sep 17 00:00:00 2001
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From: Robert Marko <robert.marko@sartura.hr>
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Date: Mon, 1 Nov 2021 18:10:28 +0100
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Subject: [PATCH] net: dsa: add Qualcomm IPQ4019 built-in switch support
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Qualcomm IPQ40xx SoC-s have a variant of QCA8337N switch built-in.
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It shares most of the stuff with its external counterpart, however it is
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modified for the SoC.
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Namely, it doesn't have second CPU port (Port 6), so it has 6 ports
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instead of 7.
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It also has no built-in PHY-s but rather requires external PSGMII based
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companion PHY-s (QCA8072 and QCA8075) for which it first needs to carry
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out calibration before using them.
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PSGMII has a SoC built-in PHY that is used to connect to the PHY-s which
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unfortunately requires some magic values as the datasheet doesnt document
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the bits that are being set or the register at all.
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Since its built-in it is MMIO like other peripherals and doesn't have its
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own MDIO bus but depends on the SoC provided one.
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CPU connection is at Port 0 and it uses some kind of a internal connection
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and no traditional RGMII/SGMII.
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It also doesn't use in-band tagging like other qca8k switches so a shinfo
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based tagger is used.
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Signed-off-by: Robert Marko <robert.marko@sartura.hr>
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---
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drivers/net/dsa/qca/Kconfig | 9 +++++++++
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drivers/net/dsa/qca/Makefile | 1 +
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2 files changed, 10 insertions(+)
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--- a/drivers/net/dsa/qca/Kconfig
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+++ b/drivers/net/dsa/qca/Kconfig
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@@ -15,3 +15,13 @@ config NET_DSA_QCA8K
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help
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This enables support for the Qualcomm Atheros QCA8K Ethernet
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switch chips.
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+
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+config NET_DSA_QCA8K_IPQ4019
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+ tristate "Qualcomm Atheros IPQ4019 built-in Ethernet switch support"
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+ depends on HAS_IOMEM && NET_DSA
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+ select NET_DSA_TAG_IPQ4019
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+ select REGMAP
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+ help
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+ This enables support for the Qualcomm Atheros IPQ4019 SoC built-in
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+ Ethernet switch.
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+
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--- a/drivers/net/dsa/qca/Makefile
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+++ b/drivers/net/dsa/qca/Makefile
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@@ -1,4 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_NET_DSA_AR9331) += ar9331.o
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+obj-$(CONFIG_NET_DSA_QCA8K_IPQ4019) += qca8k-ipq4019.o
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obj-$(CONFIG_NET_DSA_QCA8K) += qca8k.o
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qca8k-y += qca8k-common.o qca8k-8xxx.o
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