505 lines
13 KiB
Diff
505 lines
13 KiB
Diff
--- a/arch/arm/configs/ixp4xx_defconfig
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+++ b/arch/arm/configs/ixp4xx_defconfig
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@@ -26,6 +26,7 @@ CONFIG_MACH_NAS100D=y
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CONFIG_MACH_DSMG600=y
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CONFIG_MACH_FSG=y
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CONFIG_MACH_GTWX5715=y
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+CONFIG_MACH_MI424WR=y
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CONFIG_IXP4XX_QMGR=y
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CONFIG_IXP4XX_NPE=y
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# CONFIG_ARM_THUMB is not set
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--- a/arch/arm/mach-ixp4xx/Kconfig
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+++ b/arch/arm/mach-ixp4xx/Kconfig
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@@ -258,6 +258,13 @@ config MACH_MIC256
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Say 'Y' here if you want your kernel to support the MIC256
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board from OMICRON electronics GmbH.
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+config MACH_MI424WR
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+ bool "Actiontec MI424WR"
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+ depends on ARCH_IXP4XX
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+ select PCI
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+ help
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+ Add support for the Actiontec MI424-WR.
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+
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comment "IXP4xx Options"
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config IXP4XX_INDIRECT_PCI
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--- a/arch/arm/mach-ixp4xx/Makefile
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+++ b/arch/arm/mach-ixp4xx/Makefile
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@@ -25,6 +25,7 @@ obj-pci-$(CONFIG_MACH_COMPEXWP18) += ixd
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obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o
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obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o
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obj-pci-$(CONFIG_MACH_TW5334) += tw5334-pci.o
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+obj-pci-$(CONFIG_MACH_MI424WR) += mi424wr-pci.o
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obj-y += common.o
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@@ -51,6 +52,7 @@ obj-$(CONFIG_MACH_COMPEXWP18) += compex4
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obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o
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obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o
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obj-$(CONFIG_MACH_TW5334) += tw5334-setup.o
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+obj-$(CONFIG_MACH_MI424WR) += mi424wr-setup.o
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obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
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obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
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--- /dev/null
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+++ b/arch/arm/mach-ixp4xx/mi424wr-pci.c
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@@ -0,0 +1,70 @@
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+/*
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+ * arch/arm/mach-ixp4xx/mi424wr-pci.c
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+ *
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+ * Actiontec MI424WR board-level PCI initialization
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+ *
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+ * Copyright (C) 2008 Jose Vasconcellos
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+ *
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+ * Maintainer: Jose Vasconcellos <jvasco@verizon.net>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/pci.h>
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+#include <linux/init.h>
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+#include <linux/irq.h>
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+
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+#include <asm/mach-types.h>
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+#include <asm/mach/pci.h>
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+
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+/* PCI controller GPIO to IRQ pin mappings
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+ * This information was obtained from Actiontec's GPL release.
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+ *
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+ * INTA INTB
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+ * SLOT 13 8 6
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+ * SLOT 14 7 8
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+ * SLOT 15 6 7
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+ */
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+
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+void __init mi424wr_pci_preinit(void)
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+{
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+ irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
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+ irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
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+ irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
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+
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+ ixp4xx_pci_preinit();
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+}
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+
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+static int __init mi424wr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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+{
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+ if (slot == 13)
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+ return IRQ_IXP4XX_GPIO8;
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+ if (slot == 14)
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+ return IRQ_IXP4XX_GPIO7;
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+ if (slot == 15)
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+ return IRQ_IXP4XX_GPIO6;
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+
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+ return -1;
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+}
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+
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+struct hw_pci mi424wr_pci __initdata = {
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+ .nr_controllers = 1,
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+ .preinit = mi424wr_pci_preinit,
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+ .ops = &ixp4xx_ops,
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+ .setup = ixp4xx_setup,
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+ .map_irq = mi424wr_map_irq,
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+};
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+
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+int __init mi424wr_pci_init(void)
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+{
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+ if (machine_is_mi424wr())
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+ pci_common_init(&mi424wr_pci);
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+ return 0;
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+}
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+
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+subsys_initcall(mi424wr_pci_init);
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+
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--- /dev/null
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+++ b/arch/arm/mach-ixp4xx/mi424wr-setup.c
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@@ -0,0 +1,384 @@
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+/*
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+ * arch/arm/mach-ixp4xx/mi424wr-setup.c
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+ *
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+ * Actiontec MI424-WR board setup
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+ * Copyright (c) 2008 Jose Vasconcellos
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+ *
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+ * Based on Gemtek GTWX5715 by
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+ * Copyright (C) 2004 George T. Joseph
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+ * Derived from Coyote
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License
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+ * as published by the Free Software Foundation; either version 2
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+ * of the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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+ *
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+ */
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+
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+#include <linux/init.h>
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+#include <linux/device.h>
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+#include <linux/serial.h>
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+#include <linux/serial_8250.h>
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+#include <linux/types.h>
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+#include <linux/memory.h>
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+#include <linux/leds.h>
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+#include <linux/spi/spi.h>
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+#include <linux/spi/spi_gpio.h>
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+#include <linux/dma-mapping.h>
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+
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+#include <asm/setup.h>
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+#include <asm/system_info.h>
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+#include <asm/irq.h>
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+#include <asm/io.h>
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+#include <asm/mach-types.h>
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+#include <asm/mach/arch.h>
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+#include <asm/mach/flash.h>
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+
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+/*
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+ * GPIO 2,3,4 and 9 are hard wired to the Micrel/Kendin KS8995M Switch
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+ * and operate as an SPI type interface. The details of the interface
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+ * are available on Kendin/Micrel's web site.
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+ */
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+
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+#define MI424WR_KSSPI_SELECT 9
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+#define MI424WR_KSSPI_TXD 4
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+#define MI424WR_KSSPI_CLOCK 2
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+#define MI424WR_KSSPI_RXD 3
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+
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+/*
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+ * The "reset" button is wired to GPIO 10.
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+ * The GPIO is brought "low" when the button is pushed.
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+ */
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+
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+#define MI424WR_BUTTON_GPIO 10
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+#define MI424WR_BUTTON_IRQ IRQ_IXP4XX_GPIO10
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+
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+#define MI424WR_MOCA_WAN_LED 11
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+
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+/* Latch on CS1 - taken from Actiontec's 2.4 source code
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+ *
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+ * default latch value
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+ * 0 - power alarm led (red) 0 (off)
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+ * 1 - power led (green) 0 (off)
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+ * 2 - wireless led (green) 1 (off)
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+ * 3 - no internet led (red) 0 (off)
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+ * 4 - internet ok led (green) 0 (off)
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+ * 5 - moca LAN 0 (off)
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+ * 6 - WAN alarm led (red) 0 (off)
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+ * 7 - PCI reset 1 (not reset)
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+ * 8 - IP phone 1 led (green) 1 (off)
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+ * 9 - IP phone 2 led (green) 1 (off)
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+ * 10 - VOIP ready led (green) 1 (off)
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+ * 11 - PSTN relay 1 control 0 (PSTN)
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+ * 12 - PSTN relay 1 control 0 (PSTN)
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+ * 13 - N/A
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+ * 14 - N/A
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+ * 15 - N/A
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+ */
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+
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+#define MI424WR_LATCH_MASK 0x04
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+#define MI424WR_LATCH_DEFAULT 0x1f86
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+
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+#define MI424WR_LATCH_ALARM_LED 0x00
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+#define MI424WR_LATCH_POWER_LED 0x01
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+#define MI424WR_LATCH_WIRELESS_LED 0x02
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+#define MI424WR_LATCH_INET_DOWN_LED 0x03
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+#define MI424WR_LATCH_INET_OK_LED 0x04
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+#define MI424WR_LATCH_MOCA_LAN_LED 0x05
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+#define MI424WR_LATCH_WAN_ALARM_LED 0x06
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+#define MI424WR_LATCH_PCI_RESET 0x07
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+#define MI424WR_LATCH_PHONE1_LED 0x08
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+#define MI424WR_LATCH_PHONE2_LED 0x09
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+#define MI424WR_LATCH_VOIP_LED 0x10
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+#define MI424WR_LATCH_PSTN_RELAY1 0x11
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+#define MI424WR_LATCH_PSTN_RELAY2 0x12
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+
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+/* initialize CS1 to default timings, Intel style, 16-bit bus */
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+#define MI424WR_CS1_CONFIG 0x80000002
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+
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+/* Define both UARTs but they are not easily accessible.
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+ */
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+
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+static struct resource mi424wr_uart_resources[] = {
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+ {
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+ .start = IXP4XX_UART1_BASE_PHYS,
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+ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .start = IXP4XX_UART2_BASE_PHYS,
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+ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
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+ .flags = IORESOURCE_MEM,
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+ }
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+};
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+
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+
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+static struct plat_serial8250_port mi424wr_uart_platform_data[] = {
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+ {
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+ .mapbase = IXP4XX_UART1_BASE_PHYS,
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+ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
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+ .irq = IRQ_IXP4XX_UART1,
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+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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+ .iotype = UPIO_MEM,
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+ .regshift = 2,
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+ .uartclk = IXP4XX_UART_XTAL,
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+ },
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+ {
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+ .mapbase = IXP4XX_UART2_BASE_PHYS,
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+ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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+ .irq = IRQ_IXP4XX_UART2,
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+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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+ .iotype = UPIO_MEM,
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+ .regshift = 2,
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+ .uartclk = IXP4XX_UART_XTAL,
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+ },
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+ { },
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+};
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+
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+static struct platform_device mi424wr_uart_device = {
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+ .name = "serial8250",
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+ .id = PLAT8250_DEV_PLATFORM,
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+ .dev.platform_data = mi424wr_uart_platform_data,
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+ .num_resources = ARRAY_SIZE(mi424wr_uart_resources),
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+ .resource = mi424wr_uart_resources,
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+};
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+
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+static struct flash_platform_data mi424wr_flash_data = {
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+ .map_name = "cfi_probe",
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+ .width = 2,
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+};
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+
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+static struct resource mi424wr_flash_resource = {
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+ .flags = IORESOURCE_MEM,
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+};
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+
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+static struct platform_device mi424wr_flash = {
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+ .name = "IXP4XX-Flash",
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+ .id = 0,
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+ .dev.platform_data = &mi424wr_flash_data,
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+ .num_resources = 1,
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+ .resource = &mi424wr_flash_resource,
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+};
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+
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+static struct spi_gpio_platform_data mi424wr_spi_platform_data = {
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+ .sck = MI424WR_KSSPI_CLOCK,
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+ .mosi = MI424WR_KSSPI_TXD,
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+ .miso = MI424WR_KSSPI_RXD,
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+ .num_chipselect = 1,
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+};
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+
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+static struct platform_device mi424wr_spi_device = {
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+ .name = "spi-gpio",
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+ .id = 1,
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+ .dev.platform_data = &mi424wr_spi_platform_data,
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+};
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+
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+static struct spi_board_info mi424wr_spi_devices[] __initdata = {
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+ {
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+ .modalias = "spi-ks8995",
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+ .max_speed_hz = 500000,
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+ .mode = SPI_MODE_0,
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+ .bus_num = 1,
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+ .chip_select = 0,
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+ .controller_data = (void *)MI424WR_KSSPI_SELECT,
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+ }
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+};
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+
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+static struct gpio_led mi424wr_gpio_led[] = {
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+ {
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+ .name = "moca-wan", /* green led */
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+ .gpio = MI424WR_MOCA_WAN_LED,
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+ .active_low = 0,
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+ }
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+};
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+
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+static struct gpio_led_platform_data mi424wr_gpio_leds_data = {
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+ .num_leds = 1,
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+ .leds = mi424wr_gpio_led,
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+};
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+
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+static struct platform_device mi424wr_gpio_leds = {
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+ .name = "leds-gpio",
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+ .id = -1,
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+ .dev.platform_data = &mi424wr_gpio_leds_data,
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+};
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+
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+static uint16_t latch_value = MI424WR_LATCH_DEFAULT;
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+static uint16_t __iomem *iobase;
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+
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+static void mi424wr_latch_set_led(u8 bit, enum led_brightness value)
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+{
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+
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+ if (((MI424WR_LATCH_MASK >> bit) & 1) ^ (value == LED_OFF))
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+ latch_value &= ~(0x1 << bit);
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+ else
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+ latch_value |= (0x1 << bit);
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+
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+ __raw_writew(latch_value, iobase);
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+
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+}
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+
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+static struct latch_led mi424wr_latch_led[] = {
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+ {
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+ .name = "power-alarm",
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+ .bit = MI424WR_LATCH_ALARM_LED,
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+ },
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+ {
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+ .name = "power-ok",
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+ .bit = MI424WR_LATCH_POWER_LED,
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+ },
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+ {
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+ .name = "wireless", /* green led */
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+ .bit = MI424WR_LATCH_WIRELESS_LED,
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+ },
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+ {
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+ .name = "inet-down", /* red led */
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+ .bit = MI424WR_LATCH_INET_DOWN_LED,
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+ },
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+ {
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+ .name = "inet-up", /* green led */
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+ .bit = MI424WR_LATCH_INET_OK_LED,
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+ },
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+ {
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+ .name = "moca-lan", /* green led */
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+ .bit = MI424WR_LATCH_MOCA_LAN_LED,
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+ },
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+ {
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+ .name = "wan-alarm", /* red led */
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+ .bit = MI424WR_LATCH_WAN_ALARM_LED,
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+ }
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+};
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+
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+static struct latch_led_platform_data mi424wr_latch_leds_data = {
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+ .num_leds = ARRAY_SIZE(mi424wr_latch_led),
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+ .mem = 0x51000000,
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+ .leds = mi424wr_latch_led,
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+ .set_led = mi424wr_latch_set_led,
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+};
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+
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+static struct platform_device mi424wr_latch_leds = {
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+ .name = "leds-latch",
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+ .id = -1,
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+ .dev.platform_data = &mi424wr_latch_leds_data,
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+};
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+
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+static struct eth_plat_info mi424wr_wan_data = {
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+ .phy = 17, /* KS8721 */
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+ .rxq = 3,
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+ .txreadyq = 20,
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+};
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+
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+static struct eth_plat_info mi424wr_lan_data = {
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+ .phy = IXP4XX_ETH_PHY_MAX_ADDR,
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+ .phy_mask = 0x1e, /* ports 1-4 of the KS8995 switch */
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+ .rxq = 4,
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+ .txreadyq = 21,
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+};
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+
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+static struct platform_device mi424wr_npe_devices[] = {
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+ {
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+ .name = "ixp4xx_eth",
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+ .id = IXP4XX_ETH_NPEC,
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+ .dev.platform_data = &mi424wr_lan_data,
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+ .dev.coherent_dma_mask = DMA_BIT_MASK(32),
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+ }, {
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+ .name = "ixp4xx_eth",
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+ .id = IXP4XX_ETH_NPEB,
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+ .dev.platform_data = &mi424wr_wan_data,
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+ .dev.coherent_dma_mask = DMA_BIT_MASK(32),
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+ }
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+};
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+
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+static struct eth_plat_info mi424wr_wanD_data = {
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+ .phy = 5,
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+ .rxq = 4,
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+ .txreadyq = 21,
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+};
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+
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+static struct eth_plat_info mi424wr_lanD_data = {
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+ .phy = IXP4XX_ETH_PHY_MAX_ADDR,
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+ .phy_mask = 0x1e, /* ports 1-4 of the KS8995 switch */
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+ .rxq = 3,
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+ .txreadyq = 20,
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+};
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+
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+static struct platform_device mi424wr_npeD_devices[] = {
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+ {
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+ .name = "ixp4xx_eth",
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+ .id = IXP4XX_ETH_NPEB,
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+ .dev.platform_data = &mi424wr_lanD_data,
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+ .dev.coherent_dma_mask = DMA_BIT_MASK(32),
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+ }, {
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+ .name = "ixp4xx_eth",
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+ .id = IXP4XX_ETH_NPEC,
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+ .dev.platform_data = &mi424wr_wanD_data,
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+ .dev.coherent_dma_mask = DMA_BIT_MASK(32),
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+ }
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+};
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+
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+static struct platform_device *mi424wr_devices[] __initdata = {
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+ &mi424wr_uart_device,
|
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+ &mi424wr_flash,
|
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+ &mi424wr_spi_device,
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+ &mi424wr_gpio_leds,
|
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+ &mi424wr_latch_leds,
|
|
+};
|
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+
|
|
+static void __init mi424wr_init(void)
|
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+{
|
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+ ixp4xx_sys_init();
|
|
+
|
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+ mi424wr_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
|
|
+ mi424wr_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_8M - 1;
|
|
+
|
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+ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
|
|
+ *IXP4XX_EXP_CS1 = MI424WR_CS1_CONFIG;
|
|
+
|
|
+ /* configure button as input
|
|
+ */
|
|
+ gpio_line_config(MI424WR_BUTTON_GPIO, IXP4XX_GPIO_IN);
|
|
+
|
|
+ /* Initialize LEDs and enables PCI bus.
|
|
+ */
|
|
+ iobase = ioremap_nocache(IXP4XX_EXP_BUS_BASE(1), 0x1000);
|
|
+ __raw_writew(latch_value, iobase);
|
|
+
|
|
+ spi_register_board_info(mi424wr_spi_devices, ARRAY_SIZE(mi424wr_spi_devices));
|
|
+ platform_add_devices(mi424wr_devices, ARRAY_SIZE(mi424wr_devices));
|
|
+
|
|
+ /* Need to figure out how to detect revD.
|
|
+ * Look for a revision argument sent by redboot.
|
|
+ */
|
|
+#define revD 4
|
|
+ if (system_rev == revD) {
|
|
+ platform_device_register(&mi424wr_npeD_devices[0]);
|
|
+ platform_device_register(&mi424wr_npeD_devices[1]);
|
|
+ } else {
|
|
+ platform_device_register(&mi424wr_npe_devices[0]);
|
|
+ platform_device_register(&mi424wr_npe_devices[1]);
|
|
+ }
|
|
+}
|
|
+
|
|
+
|
|
+MACHINE_START(MI424WR, "Actiontec MI424WR")
|
|
+ /* Maintainer: Jose Vasconcellos */
|
|
+ .map_io = ixp4xx_map_io,
|
|
+ .init_irq = ixp4xx_init_irq,
|
|
+ .init_time = ixp4xx_timer_init,
|
|
+ .atag_offset = 0x0100,
|
|
+ .init_machine = mi424wr_init,
|
|
+#if defined(CONFIG_PCI)
|
|
+ .dma_zone_size = SZ_64M,
|
|
+#endif
|
|
+ .restart = ixp4xx_restart,
|
|
+MACHINE_END
|
|
+
|