swig has been installed on the buildbots a while a ago and Petr Štetiar got a fix for the pylibfdt error. Use that and re-enable the builds for mt7620 and mt7621. Refresh patches while at it. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
		
			
				
	
	
		
			68 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
			
		
		
	
	
			68 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
From 7237a6a0c020c05bb819774391154b40b2cfaabd Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Fri, 20 May 2022 11:23:42 +0800
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Subject: [PATCH 19/25] net: mediatek: add support for MediaTek MT7621 SoC
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This patch adds GMAC support for MediaTek MT7621 SoC.
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MT7621 has the same GMAC/Switch configuration as MT7623.
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Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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 drivers/net/mtk_eth.c | 21 +++++++++++++++------
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 1 file changed, 15 insertions(+), 6 deletions(-)
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--- a/drivers/net/mtk_eth.c
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+++ b/drivers/net/mtk_eth.c
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@@ -145,7 +145,8 @@ enum mtk_switch {
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 enum mtk_soc {
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 	SOC_MT7623,
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 	SOC_MT7629,
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-	SOC_MT7622
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+	SOC_MT7622,
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+	SOC_MT7621
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 };
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 struct mtk_eth_priv {
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@@ -675,12 +676,18 @@ static int mt7530_pad_clk_setup(struct m
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 static int mt7530_setup(struct mtk_eth_priv *priv)
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 {
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 	u16 phy_addr, phy_val;
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-	u32 val;
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+	u32 val, txdrv;
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 	int i;
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-	/* Select 250MHz clk for RGMII mode */
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-	mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG,
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-		       ETHSYS_TRGMII_CLK_SEL362_5, 0);
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+	if (priv->soc != SOC_MT7621) {
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+		/* Select 250MHz clk for RGMII mode */
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+		mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG,
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+			       ETHSYS_TRGMII_CLK_SEL362_5, 0);
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+
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+		txdrv = 8;
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+	} else {
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+		txdrv = 4;
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+	}
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 	/* Modify HWTRAP first to allow direct access to internal PHYs */
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 	mt753x_reg_read(priv, HWTRAP_REG, &val);
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@@ -738,7 +745,8 @@ static int mt7530_setup(struct mtk_eth_p
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 	/* Lower Tx Driving for TRGMII path */
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 	for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
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 		mt753x_reg_write(priv, MT7530_TRGMII_TD_ODT(i),
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-				 (8 << TD_DM_DRVP_S) | (8 << TD_DM_DRVN_S));
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+				 (txdrv << TD_DM_DRVP_S) |
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+				 (txdrv << TD_DM_DRVN_S));
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 	for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
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 		mt753x_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16);
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@@ -1540,6 +1548,7 @@ static const struct udevice_id mtk_eth_i
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 	{ .compatible = "mediatek,mt7629-eth", .data = SOC_MT7629 },
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 	{ .compatible = "mediatek,mt7623-eth", .data = SOC_MT7623 },
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 	{ .compatible = "mediatek,mt7622-eth", .data = SOC_MT7622 },
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+	{ .compatible = "mediatek,mt7621-eth", .data = SOC_MT7621 },
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 	{}
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 };
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