65 lines
1.7 KiB
Diff
65 lines
1.7 KiB
Diff
From b1b3c3d2ce62872c8dec4a7d645af6b3c565e094 Mon Sep 17 00:00:00 2001
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From: Sam Shih <sam.shih@mediatek.com>
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Date: Mon, 20 Apr 2020 17:11:32 +0800
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Subject: [PATCH 2/3] mt7622 uboot: add dts and config for spi nand
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This patch add dts and config for mt7622 spi nand
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Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
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---
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arch/arm/dts/mt7622-rfb.dts | 6 ++++++
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arch/arm/dts/mt7622.dtsi | 20 ++++++++++++++++++++
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2 files changed, 26 insertions(+)
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diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts
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index f05c3fe14d..05502bddec 100644
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--- a/arch/arm/dts/mt7622-rfb.dts
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+++ b/arch/arm/dts/mt7622-rfb.dts
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@@ -143,6 +143,12 @@
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};
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};
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+&nandc {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&snfi_pins>;
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+ status = "okay";
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+};
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+
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
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index 1e8ec9b48b..63fdb63d4a 100644
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--- a/arch/arm/dts/mt7622.dtsi
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+++ b/arch/arm/dts/mt7622.dtsi
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@@ -52,6 +52,26 @@
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#size-cells = <0>;
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};
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+ nandc: nfi@1100d000 {
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+ compatible = "mediatek,mt7622-nfc";
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+ reg = <0x1100d000 0x1000>,
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+ <0x1100e000 0x1000>;
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+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_NFI_PD>,
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+ <&pericfg CLK_PERI_NFIECC_PD>,
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+ <&pericfg CLK_PERI_SNFI_PD>,
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+ <&topckgen CLK_TOP_NFI_INFRA_SEL>,
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+ <&topckgen CLK_TOP_UNIVPLL2_D8>;
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+ clock-names = "nfi_clk",
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+ "ecc_clk",
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+ "snfi_clk",
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+ "spinfi_sel",
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+ "spinfi_parent_50m";
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+ nand-ecc-mode = "hw";
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+ status = "disabled";
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+ };
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+
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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--
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2.17.1
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