16031ebaf8
AR934x chips also got the 'old' qca,ar9330-uart in addition to the 'new' ns16550a compatible one. Add support for UART1 clock selector as well as device-tree bindings in ar934x.dtsi to make use of that uart. Reported-by: Piotr Dymacz <pepe2k@gmail.com> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
53 lines
1.7 KiB
Diff
53 lines
1.7 KiB
Diff
--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -42,6 +42,7 @@ static const char * const clk_names[ATH7
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[ATH79_CLK_AHB] = "ahb",
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[ATH79_CLK_REF] = "ref",
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[ATH79_CLK_MDIO] = "mdio",
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+ [ATH79_CLK_UART1] = "uart1",
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};
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static const char * __init ath79_clk_name(int type)
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@@ -346,6 +347,9 @@ static void __init ar934x_clocks_init(vo
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if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
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ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
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+ if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL)
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+ ath79_set_clk(ATH79_CLK_UART1, 100 * 1000 * 1000);
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+
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iounmap(dpll_base);
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}
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@@ -651,6 +655,9 @@ static void __init ath79_clocks_init_dt(
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if (!clks[ATH79_CLK_MDIO])
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clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
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+ if (!clks[ATH79_CLK_UART1])
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+ clks[ATH79_CLK_UART1] = clks[ATH79_CLK_REF];
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+
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if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
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pr_err("%pOF: could not register clk provider\n", np);
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goto err_iounmap;
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -351,6 +351,7 @@
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
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#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
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+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL BIT(7)
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#define QCA953X_PLL_CPU_CONFIG_REG 0x00
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#define QCA953X_PLL_DDR_CONFIG_REG 0x04
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--- a/include/dt-bindings/clock/ath79-clk.h
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+++ b/include/dt-bindings/clock/ath79-clk.h
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@@ -15,7 +15,8 @@
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#define ATH79_CLK_AHB 2
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#define ATH79_CLK_REF 3
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#define ATH79_CLK_MDIO 4
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+#define ATH79_CLK_UART1 5
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-#define ATH79_CLK_END 5
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+#define ATH79_CLK_END 6
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#endif /* __DT_BINDINGS_ATH79_CLK_H */
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