e0e74d8a2c
swig has been installed on the buildbots a while a ago and Petr Štetiar got a fix for the pylibfdt error. Use that and re-enable the builds for mt7620 and mt7621. Refresh patches while at it. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
112 lines
3.4 KiB
Diff
112 lines
3.4 KiB
Diff
From be570e7b0ce004127a7cc97bfae30037fc42a340 Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Fri, 20 May 2022 11:21:39 +0800
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Subject: [PATCH 02/25] mips: add more definitions for asm/cm.h
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This patch add more definitions needed for MT7621 initialization.
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MT7621 needs to initialize GIC/CPC and other related parts.
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Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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arch/mips/include/asm/cm.h | 67 ++++++++++++++++++++++++++++++++++++++
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1 file changed, 67 insertions(+)
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--- a/arch/mips/include/asm/cm.h
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+++ b/arch/mips/include/asm/cm.h
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@@ -8,9 +8,23 @@
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#define __MIPS_ASM_CM_H__
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/* Global Control Register (GCR) offsets */
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+#define GCR_CONFIG 0x0000
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#define GCR_BASE 0x0008
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#define GCR_BASE_UPPER 0x000c
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+#define GCR_CONTROL 0x0010
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+#define GCR_ACCESS 0x0020
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#define GCR_REV 0x0030
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+#define GCR_GIC_BASE 0x0080
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+#define GCR_CPC_BASE 0x0088
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+#define GCR_REG0_BASE 0x0090
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+#define GCR_REG0_MASK 0x0098
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+#define GCR_REG1_BASE 0x00a0
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+#define GCR_REG1_MASK 0x00a8
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+#define GCR_REG2_BASE 0x00b0
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+#define GCR_REG2_MASK 0x00b8
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+#define GCR_REG3_BASE 0x00c0
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+#define GCR_REG3_MASK 0x00c8
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+#define GCR_CPC_STATUS 0x00f0
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#define GCR_L2_CONFIG 0x0130
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#define GCR_L2_TAG_ADDR 0x0600
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#define GCR_L2_TAG_ADDR_UPPER 0x0604
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@@ -19,10 +33,59 @@
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#define GCR_L2_DATA 0x0610
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#define GCR_L2_DATA_UPPER 0x0614
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#define GCR_Cx_COHERENCE 0x2008
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+#define GCR_Cx_OTHER 0x2018
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+#define GCR_Cx_ID 0x2028
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+#define GCR_CO_COHERENCE 0x4008
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+
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+/* GCR_CONFIG fields */
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+#define GCR_CONFIG_NUM_CLUSTERS_SHIFT 23
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+#define GCR_CONFIG_NUM_CLUSTERS (0x7f << 23)
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+#define GCR_CONFIG_NUMIOCU_SHIFT 8
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+#define GCR_CONFIG_NUMIOCU (0xff << 8)
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+#define GCR_CONFIG_PCORES_SHIFT 0
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+#define GCR_CONFIG_PCORES (0xff << 0)
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+
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+/* GCR_BASE fields */
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+#define GCR_BASE_SHIFT 15
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+#define CCA_DEFAULT_OVR_SHIFT 5
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+#define CCA_DEFAULT_OVR_MASK (0x7 << 5)
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+#define CCA_DEFAULT_OVREN (0x1 << 4)
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+#define CM_DEFAULT_TARGET_SHIFT 0
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+#define CM_DEFAULT_TARGET_MASK (0x3 << 0)
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+
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+/* GCR_CONTROL fields */
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+#define GCR_CONTROL_SYNCCTL (0x1 << 16)
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/* GCR_REV CM versions */
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#define GCR_REV_CM3 0x0800
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+/* GCR_GIC_BASE fields */
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+#define GCR_GIC_BASE_ADDRMASK_SHIFT 7
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+#define GCR_GIC_BASE_ADDRMASK (0x1ffffff << 7)
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+#define GCR_GIC_EN (0x1 << 0)
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+
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+/* GCR_CPC_BASE fields */
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+#define GCR_CPC_BASE_ADDRMASK_SHIFT 15
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+#define GCR_CPC_BASE_ADDRMASK (0x1ffff << 15)
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+#define GCR_CPC_EN (0x1 << 0)
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+
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+/* GCR_REGn_MASK fields */
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+#define GCR_REGn_MASK_ADDRMASK_SHIFT 16
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+#define GCR_REGn_MASK_ADDRMASK (0xffff << 16)
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+#define GCR_REGn_MASK_CCAOVR_SHIFT 5
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+#define GCR_REGn_MASK_CCAOVR (0x7 << 5)
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+#define GCR_REGn_MASK_CCAOVREN (1 << 4)
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+#define GCR_REGn_MASK_DROPL2 (1 << 2)
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+#define GCR_REGn_MASK_CMTGT_SHIFT 0
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+#define GCR_REGn_MASK_CMTGT (0x3 << 0)
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+#define GCR_REGn_MASK_CMTGT_DISABLED 0x0
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+#define GCR_REGn_MASK_CMTGT_MEM 0x1
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+#define GCR_REGn_MASK_CMTGT_IOCU0 0x2
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+#define GCR_REGn_MASK_CMTGT_IOCU1 0x3
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+
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+/* GCR_CPC_STATUS fields */
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+#define GCR_CPC_EX (0x1 << 0)
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+
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/* GCR_L2_CONFIG fields */
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#define GCR_L2_CONFIG_ASSOC_SHIFT 0
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#define GCR_L2_CONFIG_ASSOC_BITS 8
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@@ -36,6 +99,10 @@
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#define GCR_Cx_COHERENCE_DOM_EN (0xff << 0)
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#define GCR_Cx_COHERENCE_EN (0x1 << 0)
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+/* GCR_Cx_OTHER fields */
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+#define GCR_Cx_OTHER_CORENUM_SHIFT 16
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+#define GCR_Cx_OTHER_CORENUM (0xffff << 16)
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+
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#ifndef __ASSEMBLY__
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#include <asm/io.h>
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