c68c71eaa9
Update patch with version submitted upstream. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
123 lines
3.8 KiB
Diff
123 lines
3.8 KiB
Diff
From 73d20ebc21c562fbe79d02fa0fa38e095e716fa9 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Wed, 19 Apr 2023 20:25:51 +0100
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Subject: [PATCH] pwm: mediatek: Add support for MT7981
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The PWM unit on MT7981 uses different register offsets than previous
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MediaTek PWM units. Add support for these new offsets and add support
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for PWM on MT7981 which has 3 PWM channels, one of them is typically
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used for a temperature controlled fan.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/pwm/pwm-mediatek.c | 41 ++++++++++++++++++++++++++++++--------
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1 file changed, 33 insertions(+), 8 deletions(-)
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--- a/drivers/pwm/pwm-mediatek.c
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+++ b/drivers/pwm/pwm-mediatek.c
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@@ -38,6 +38,7 @@ struct pwm_mediatek_of_data {
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unsigned int num_pwms;
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bool pwm45_fixup;
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bool has_ck_26m_sel;
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+ const unsigned int *reg_offset;
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};
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/**
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@@ -59,10 +60,14 @@ struct pwm_mediatek_chip {
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const struct pwm_mediatek_of_data *soc;
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};
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-static const unsigned int pwm_mediatek_reg_offset[] = {
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+static const unsigned int mtk_pwm_reg_offset_v1[] = {
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0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
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};
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+static const unsigned int mtk_pwm_reg_offset_v2[] = {
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+ 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
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+};
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+
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static inline struct pwm_mediatek_chip *
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to_pwm_mediatek_chip(struct pwm_chip *chip)
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{
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@@ -111,7 +116,7 @@ static inline void pwm_mediatek_writel(s
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unsigned int num, unsigned int offset,
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u32 value)
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{
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- writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
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+ writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
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}
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static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
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@@ -270,48 +275,63 @@ static const struct pwm_mediatek_of_data
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.num_pwms = 8,
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.pwm45_fixup = false,
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.has_ck_26m_sel = false,
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+ .reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct pwm_mediatek_of_data mt7622_pwm_data = {
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.num_pwms = 6,
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.pwm45_fixup = false,
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.has_ck_26m_sel = true,
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+ .reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct pwm_mediatek_of_data mt7623_pwm_data = {
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.num_pwms = 5,
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.pwm45_fixup = true,
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.has_ck_26m_sel = false,
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+ .reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct pwm_mediatek_of_data mt7628_pwm_data = {
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.num_pwms = 4,
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.pwm45_fixup = true,
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.has_ck_26m_sel = false,
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+ .reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct pwm_mediatek_of_data mt7629_pwm_data = {
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.num_pwms = 1,
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.pwm45_fixup = false,
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.has_ck_26m_sel = false,
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+ .reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct pwm_mediatek_of_data mt8183_pwm_data = {
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.num_pwms = 4,
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.pwm45_fixup = false,
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.has_ck_26m_sel = true,
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+ .reg_offset = mtk_pwm_reg_offset_v1,
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+};
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+
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+static const struct pwm_mediatek_of_data mt7981_pwm_data = {
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+ .num_pwms = 3,
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+ .pwm45_fixup = false,
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+ .has_ck_26m_sel = true,
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+ .reg_offset = mtk_pwm_reg_offset_v2,
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};
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static const struct pwm_mediatek_of_data mt7986_pwm_data = {
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.num_pwms = 2,
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.pwm45_fixup = false,
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.has_ck_26m_sel = true,
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+ .reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct pwm_mediatek_of_data mt8516_pwm_data = {
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.num_pwms = 5,
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.pwm45_fixup = false,
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.has_ck_26m_sel = true,
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+ .reg_offset = mtk_pwm_reg_offset_v1,
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};
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static const struct of_device_id pwm_mediatek_of_match[] = {
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@@ -320,6 +340,7 @@ static const struct of_device_id pwm_med
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{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
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{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
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{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
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+ { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
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{ .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
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{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
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{ .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
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