Initial commit

target/linux/starfive/patches-6.6/1019-riscv-dts-starfive-Add-JH7100-cache-controller.patch

@@ -0,0 +1,50 @@
+From e1918356dcc285eb7c50f271795e6fcc18d6c092 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
+Date: Thu, 30 Nov 2023 16:19:28 +0100
+Subject: [PATCH 1019/1024] riscv: dts: starfive: Add JH7100 cache controller
+
+The StarFive JH7100 SoC also features the SiFive L2 cache controller,
+so add the device tree nodes for it.
+
+Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
+Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
+---
+ arch/riscv/boot/dts/starfive/jh7100.dtsi | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
++++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
+@@ -32,6 +32,7 @@
+ 			i-tlb-sets = <1>;
+ 			i-tlb-size = <32>;
+ 			mmu-type = "riscv,sv39";
++			next-level-cache = <&ccache>;
+ 			riscv,isa = "rv64imafdc";
+ 			tlb-split;
+ 
+@@ -57,6 +58,7 @@
+ 			i-tlb-sets = <1>;
+ 			i-tlb-size = <32>;
+ 			mmu-type = "riscv,sv39";
++			next-level-cache = <&ccache>;
+ 			riscv,isa = "rv64imafdc";
+ 			tlb-split;
+ 
+@@ -148,6 +150,17 @@
+ 					       &cpu1_intc 3 &cpu1_intc 7>;
+ 		};
+ 
++		ccache: cache-controller@2010000 {
++			compatible = "starfive,jh7100-ccache", "sifive,ccache0", "cache";
++			reg = <0x0 0x2010000 0x0 0x1000>;
++			interrupts = <128>, <130>, <131>, <129>;
++			cache-block-size = <64>;
++			cache-level = <2>;
++			cache-sets = <2048>;
++			cache-size = <2097152>;
++			cache-unified;
++		};
++
+ 		plic: interrupt-controller@c000000 {
+ 			compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
+ 			reg = <0x0 0xc000000 0x0 0x4000000>;