ERROR: Input tree has errors, aborting (use -f to force output)
arch/arm/boot/dts/qcom-ipq8064.dtsi:1686.14-1698.5: ERROR (phandle_references): /soc/amba/nss-common: Reference to non-existent node or label "smb208_s1b"
Read back the reset register in order to flush the cache. This fixes
spurious reboot hangs on TP-Link TL-WDR3600 and TL-WDR4300 with Zentel
DRAM chips.
This issue was fixed in the past, but switching to the reset-driver
specific implementation removed the cache barrier which was previously
implicitly added by reading back the register in question.
Link: https://github.com/freifunk-gluon/gluon/issues/2904
Link: https://github.com/openwrt/openwrt/issues/13043
Link: https://dev.archive.openwrt.org/ticket/17839
Link: f8a7bfe1cb2c ("MIPS: ath79: fix system restart")
Signed-off-by: David Bauer <mail@david-bauer.net>
(cherry picked from commit 2fe8ecd880396b5ae25fe9583aaa1d71be0b8468)
Hardware
--------
CPU: Qualcomm Atheros QCA9563
RAM: 128M DDR2
FLASH: 16MB SPI-NOR
WiFi: Qualcomm Atheros QCA9563 2x2:2 802.11n 2.4GHz
Qualcomm Atheros QCA9880 2x2:2 802.11ac 5GHz
Antennas
--------
The device features internal antennas as well as external antenna
connectors. By default, the internal antennas are used.
Two GPIOs are exported by name, which can be used to control the
antenna-path mux. Writing a logical 0 enables the external antenna
connectors.
Installation
------------
1. Download the OpenWrt sysupgrade image to the device. You can use scp
for this task. The default username and password are "ubnt" and the
device is reachable at 192.168.1.20.
$ scp -O openwrt-sysupgrade.bin ubnt@192.168.1.20:/tmp/firmware.bin
2. Connect to the device using SSH.
$ ssh ubnt@192.168.1.20
3. Disable the write-protect
$ echo "5edfacbf" > /proc/ubnthal/.uf
4. Verify kernel0 and kernel1 match mtd2 and mtd3
$ cat /proc/mtd
5. Write the sysupgrade image to kernel0 and kernel1
$ dd if=/tmp/firmware.bin of=/dev/mtdblock2
$ dd if=/tmp/firmware.bin of=/dev/mtdblock3
6. Write the bootselect flag to boot from kernel0
$ dd if=/dev/zero bs=1 count=1 of=/dev/mtd4
7. Reboot the device
$ reboot
Signed-off-by: David Bauer <mail@david-bauer.net>
(cherry picked from commit bf94e0a38389b2ce5d33be9c97d104d36dd5ebd6)
This allows us to embrace alphabetical sorting for the UK-Ultra.
Signed-off-by: David Bauer <mail@david-bauer.net>
(cherry picked from commit c9e58f85f6e5d96711291f079413d2f34c36fdc3)
Setting/clearing bits on the first byte of the mac address causes collisions
when using multiple SSIDs on both PHYs. Change the allocation to alter the
last byte instead.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
(cherry picked from commit 38bec08e87b69212daf34eac7b26d643a92d9353)
Fixes a race condition that can lead to a hostapd crash
Signed-off-by: Felix Fietkau <nbd@nbd.name>
(cherry picked from commit d864f68232e910f2c8ab06a66347fc08c257dfcc)
Frequent crashes have been observed on MT7916 based platforms. While the
root of these crashes are currently unknown, they happen when decoding
rate information of connected STAs in AP mode. The rate-information is
associated with a band which is not available on the PHY.
Check for this condition in order to avoid crashing the whole system.
This patch should be removed once the roout cause has been found and
fixed.
Link: https://github.com/freifunk-gluon/gluon/issues/2980
Signed-off-by: David Bauer <mail@david-bauer.net>
(cherry picked from commit 1278d47beaabaa963b2956e81936269b7fea4003)
Adjust LED names and provide the OpenWrt status indicator aliases
to actually use LEDs by the OpenWrt boot & sysupgrade processes.
* Name both LEDs clearly by the color
* Add the missing OpenWrt LED status indicator aliases and
remove the now unnecessary default status from blue LED
After this commit, the LEDs are used as:
* bootloader, really early Linux boot: blue LED is on
* preinit/failsafe: white LED blinks rapidly
* late boot: white LED blinks slowly
* boot completed, running normally: blue LED is on
* sysupgrade: white LED blinks
Signed-off-by: Hannu Nyman <hannu.nyman@iki.fi>
(cherry picked from commit 5a82bb909bf16786b85508d2e974ddf0a14bb10c)
The COVR-X1860 are MT7621-based AX1800 devices (similar to DAP-X1860, but
with two Ethernet ports and external power supply) that are sold in sets
of two (COVR-X1862) and three (COVR-X1863).
Specification:
- MT7621
- MT7915 + MT7975 2x2 802.11ax (DBDC)
- 256MB RAM
- 128 MB flash
- 3 LEDs (red, orange, white), routed to one indicator in the top of the device
- 2 buttons (WPS in the back and Reset at the bottom of the device)
MAC addresses:
- LAN MAC (printed on the device) is stored in config2 partition as ASCII (entry factory_mac=xx:xx:xx:xx:xx:xx)
- WAN MAC: LAN MAC + 3
- 2.4G MAC: LAN MAC + 1
- 5G MAC: LAN MAC + 2
The pins for the serial console are already labeled on the board (VCC, TX, RX, GND). Serial settings: 3.3V, 115200,8n1
Flashing via OEM Web Interface:
- Download openwrt-ramips-mt7621-dlink_covr-x1860-a1-squashfs-factory.bin via the OEM web interface firmware update
- The configuration wizard can be skipped by directly going to http://192.168.0.1/UpdateFirmware_Simple.html
Flashing via Recovery Web Interface:
- Set your IP address to 192.168.0.10, subnetmask 255.255.255.0
- Press the reset button while powering on the deivce
- Keep the reset button pressed until the status LED blinks red
- Open a Chromium based browser and goto http://192.168.0.1
- Download openwrt-ramips-mt7621-dlink_covr-x1860-a1-squashfs-recovery.bin
Revert back to stock using the Recovery Web Interface:
- Set your IP address to 192.168.0.10, subnetmask 255.255.255.25
- Press the reset button while powering on the deivce
- Keep the reset button pressed until the status LED blinks red
- Open a Chromium based browser and goto http://192.168.0.1
- Flash a decrypted firmware image from D-Link. Decrypting an firmware image is described below.
Decrypting a D-Link firmware image:
- Download https://github.com/openwrt/firmware-utils/blob/master/src/dlink-sge-image.c and https://raw.githubusercontent.com/openwrt/firmware-utils/master/src/dlink-sge-image.h
- Compile a binary from the downloaded file, e.g. gcc dlink-sge-image.c -lcrypto -o dlink-sge-image
- Run ./dlink-sge-image COVR-X1860 <OriginalFirmware> <OutputFile> -d
- Example for firmware 102b01: ./dlink-sge-image COVR-X1860 COVR-X1860_RevA_Firmware_102b01.bin COVR-X1860_RevA_Firmware_102b01_Decrypted.bin -d
The pull request is based on the discussion in https://forum.openwrt.org/t/add-support-for-d-link-covr-x1860
Signed-off-by: Sebastian Schaper <openwrt@sebastianschaper.net>
Signed-off-by: Roland Reinl <reinlroland+github@gmail.com>
(cherry picked from commit 0a18259e4aa361cd9e5848c038be4b9f4e3bfcc6)
Signed-off-by: Florian Maurer <f.maurer@outlook.de>
creates SGE encrypted factory images
to use via the D-Link web interface
rename the old factory unencrypted images to recovery
for use in the recovery console when recovery is needed
adjusted to not touch unrelated devices
Signed-off-by: Alan Luck <luckyhome2008@gmail.com>
(cherry picked and adjusted from commit 4c0dc68f466588bb2ef60b29a4d8052b34112ca6)
Signed-off-by: Florian Maurer <f.maurer@outlook.de>
Patch "firmware-utils: ptgen: add SiFive GPT partition support" was
included as a separate change in 23.05. Now that we have a maintenance
branch for firmware-utils, the patch can be backported there and
included with other changes.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
MT7621 gets a new PCIe driver in the 5.15+ kernel. Allocating wrong PCIe
port will cause the PCIe NIC to not work properly. This commit fixes
the wrong port numbers on Unielec u7621-01.
According to the bootlog, MT7612E (5 GHz) is connected to pcie2, and
MT7603E (2 GHz) is connected to pcie1:
[ 1.294844] mt7621-pci 1e140000.pcie: pcie0 no card, disable it (RST & CLK)
[ 1.308635] mt7621-pci 1e140000.pcie: PCIE1 enabled
[ 1.318277] mt7621-pci 1e140000.pcie: PCIE2 enabled
Also correct the led activity for the MT7603e - not used on the MT7612e
Signed-off-by: David Bentham <db260179@gmail.com>
(cherry picked from commit 39e55bdbe27a09579658178796a9b732e126e703)
Signed-off-by: David Bentham <db260179@gmail.com>
The default strength is not enough to provide stable connection
under 3.3v LDO voltage.
Fixes: 3f3586a06d ("rockchip: add Orange Pi R1 Plus LTS support")
Fixes: #13117Fixes: #13759
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
(cherry picked from commit 3645ac8a10d9abb1451343beaf7d65b53eeecffd)
[rebased onto openwrt-23.05 branch]
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
The rt305x series SOC have two UART devices,
and the one at bus address 0x500 is disabled by default.
Some boards do not even have a pinout for the first one,
so use the same one that the kernel uses at 0xc00 instead.
This allows the lzma-loader printing to be visible
alongside the kernel log in the same console.
Tested-by: Lech Perczak <lech.perczak@gmail.com> # zte,mf283plus
Signed-off-by: Michael Pratt <mcpratt@pm.me>
(cherry picked from commit bc00c78b4338779ca1b7cd08411f76218d1f3205)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Before this was reworked, in the file for mt7621 subtarget
(target/linux/ramips/image/lzma-loader/src/board-mt7621.c)
the "Transmitter shift register empty" bit TEMT was used instead of
the "Transmitter holding register empty" bit THRE,
but after the rework, this value was labeled as the THRE bit instead.
Functionally there is no difference, but this is confusing to read,
as it suggests that the subtargets have different bits for the same
register in UART when in reality they are exactly the same.
One can use either bit, or both, at user's descretion
in order to determine whether the UART TX buffer is ready.
The generic kernel early-printk uses both,
(arch/mips/kernel/early_printk_8250.c)
while the ralink-specific early-printk uses only THRE,
(arch/mips/ralink/early_printk.c).
Define both bits and rewrite macros for readability,
keep the same values, as changing which to use should be tested first.
Ref: c31319b66 ("ramips: lzma-loader: Refactor loader")
Signed-off-by: Michael Pratt <mcpratt@pm.me>
(cherry picked from commit 2e47913c644c59aa25fbac2bc6c4297956406b82)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
The native bus address for UART was entered for rt305x UART_BASE,
but the bootloaders have memory space remapped with the same
virtual memory map the kernel uses for program addressing at boot time.
In UBoot, the remapped address is often defined as TEXT_BASE.
In the kernel, for rt305x this remapped address is RT305X_SYSC_BASE.
(arch/mips/include/asm/mach-ralink/rt305x.h)
Because the ralink I/O busses begin at a low address of 0x10000000,
they are remapped using KSEG0 or KSEG1, which for all 32-bit MIPS SOCs
(arch/mips/include/asm/addrspace.h)
are offsets of 0x80000000 and 0xa0000000 respectively.
This is consistent with the other UART_BASE macros here
and with MIPS memory map documentation.
Before the recent rework of the lzma-loader for ramips,
the original board-$(PLATFORM).c files also did not
use KSEG1ADDR for UART_BASE despite being defined,
which made this mistake easier to occur.
Fix this by defining KSEG1ADDR again and actually use it.
Copy and paste from the kernel's macros for consistency.
Link: https://training.mips.com/basic_mips/PDF/Memory_Map.pdf
Fixes: c31319b66 ("ramips: lzma-loader: Refactor loader")
Reported-by: Lech Perczak <lech.perczak@gmail.com>
Signed-off-by: Michael Pratt <mcpratt@pm.me>
(cherry picked from commit 4c1e9bd8581e01793b26f3bc964975311450ece0)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
The ESW core needs to be reset together with FE core, so after the
relevant reset controller lines are moved under FE, drop rst_esw and all
related code, which would not execute anyway, because rst_esw would be
NULL. While at that, ensure that if reset line for EPHY cannot be
claimed, a proper error message is reported.
Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Co-developed-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
[Split out of the bigger commit, provide commit mesage, refactor error
handling]
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
(cherry picked from commit f393ffcac163926bf9dbbda47c25cc7809952609)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Failing to do so will cause the DMA engine to not initialize properly
and fail to forward packets between them, and in some cases will cause
spurious transmission with size exceeding allowed packet size, causing a
kernel panic.
Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
[Provide commit description, split into logical changes]
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
(cherry picked from commit f87b66507e9245e6e02dbc76e2e7b27c9e0bf364)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Failing to do so will cause the DMA engine to not initialize properly
and fail to forward packets between them, and in some cases will cause
spurious transmission with size exceeding allowed packet size, causing a
kernel panic.
This is behaviour of downstream driver as well, however I
haven't observed bug reports about this SoC in the wild, so this
commit's purpose is to align this chip with all other SoC's - MT7620
were already using this arrangement.
Fixes: #9284
Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
(cherry picked from commit fc92fecfc7ddf19bbfd7d1305a29c666f00543af)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Failing to do so will cause the DMA engine to not initialize properly
and fail to forward packets between them, and in some cases will cause
spurious transmission with size exceeding allowed packet size, causing a
kernel panic.
This is behaviour of downstream driver as well, however I
haven't observed bug reports about this SoC in the wild, so this
commit's purpose is to align this chip with all other SoC's - MT7620
were already using this arrangement.
Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
(cherry picked from commit c5a399f372535886582f89f3da624ae7465c8ff4)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Failing to do so will cause the DMA engine to not initialize properly
and fail to forward packets between them, and in some cases will cause
spurious transmission with size exceeding allowed packet size, causing a
kernel panic.
Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
[Provide commit description, split into logical changes]
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
(cherry picked from commit 8d75b1de0ff7b9e9e0138f822a5475bb8ad7fedf)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Enabling the FE core too early causes the system to hang during boot
uncondtionally, after the reset is released. Increate it to 1-1.2ms
range.
Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
[Split previous commit, provide rationale]
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
(cherry picked from commit 7eb0458c1f7e4f681b16d2721cfc3fcb69774c95)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Use devm_reset_control_array_get_exclusive to register multiple
reset lines in FE driver. This is required to reattach ESW reset to FE
driver again, based on device tree bindings.
While at that, remove unused fe_priv.rst_ppe field, and add error
message if getting the reset fails.
Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Co-developed-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
[Split out of the bigger commit, provide commit mesage, refactor error
handling]
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
(cherry picked from commit 3f1be8edee29fe79fc33c88cbd9d647a490410e5)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
